A) Field of the Invention
This invention relates to a solid state imaging apparatus, and more in detail, a driving method of a solid state imaging apparatus.
B) Description of the Related Art
FIG. 15 is a schematic view showing a structure of a conventional solid state imaging apparatus 10.
The solid state imaging apparatus 10 includes at least a multiplicity of photoelectric conversion elements (photodiodes) 11 arranged in two-dimension, a plurality columns of vertical electric charge transfer devices (vertical charge coupled device: VCCD) 12 vertically transferring signal electric charges generated in the photoelectric conversion elements 11, horizontal electric charge transfer devices (horizontal charge coupled device: HCCD) 14a and 14b positioned at a downstream end of the columns of the VCCD 12 and horizontally transferring the signal electric charges transferred by the VCCD12, and output amplifiers 15a and 15b detecting signals output from HCCD 14a and 14b respectively. The HCCD 14a and 14b have different transfer directions from a point where the number of the columns of the VCCD 12 is divided to about a half. Further, each of the VCCD 12 and the HCCD 14a and 14b is consisted of a charge coupled device (CCD).
The HCCD in the solid state imaging apparatus using a general electric charge coupled device transfers signal electric charges to one direction, and a single output amplifier corresponding to that will be prepared; however, this conventional solid state imaging apparatus equips with two HCCD 14a and 14b transferring to different directions for improvement in speed of reading cycle of the signal electric charges.
For example, driving waveforms φV1 to φV4 in the timing chart shown in FIG. 16 are imposed on each one of the V1 to V4 in the VCCD 12. The driving waveforms φV1 to φV4 are well-known four-phase driving type and read out the signal electric charges accumulated in the photoelectric conversion elements 11 to the VCCD 12 via a reading unit 3g corresponding to the amount of light irradiated to the solid state imaging apparatus 10.
The read signal electric charges are sequentially transferred to the direction of the HCCD 14 by sequentially imposing mid-level (VM) pulse or low-level (VL) pulse on the V1 to the V4 in the VCCD 12 during the transferring period.
The HCCD 14a and 14b sequentially and horizontally transfer the signal electric charges to the direction of the output amplifiers 15 by the well-known two-phase driving method. The transferred signal electric charges are detected by the output amplifiers 15a and 15b to generate output voltage corresponding to the amount of the irradiated light as the OS waveform.
Since the transfer operations by the above-described HCCD 14a and 14b are executed at the same time, the reading period will be about a half of that in the structure having only one HCCD, and the reading cycle can be shortened.
FIG. 17 is a schematic plan view of a border between the HCCD 14a and 14b including the vertical CCD (VCCD) 12 in the conventional solid state imaging apparatus shown in FIG. 15.
The VCCD 12 has a four-phase driving system, and the odd numbered electrodes V1 and V3 are consisted of the second layer electrodes 7, and the even numbered electrodes V2 and V4 are consisted of the first layer electrodes 6. The HCCD 14 (14a and 14b) consist an interface with the last electrodes of the VCCD 12 by the second layer electrodes 7 and temporally accumulate the signal electric charges in a channel 3 under the first layer electrodes 6 via this second layer electrodes.
FIG. 18 is a cross sectional view of a part cut across a line A-B in FIG. 17.
A well layer 2 having a reverse conductive type of the substrate is formed on the surface of the one conductive type semiconductor substrate 1, and impurity layers (transfer channels) 3 and 4 having a reverse conductive type of the well layer 2 are formed on the surface of the substrate in the well layer 2. The impurity layer 4 relatively composes thin impurity layer comparing to the impurity layer 3. The first electrode 6 is formed on the substrate 1 via an insulating layer 5, and the second electrode 7 is formed on the substrate 1 and a part of the first electrode 6 via the insulating layer 5. The impurity layer 3 under the electrode 6 and the impurity layer 4 under the electrode 7 are formed. The first electrode 7 and the second electrode 8 are electrically connected, and the well-known two-phase driving CCD operation is realized by the input shown in FIG. 19.
Connection of the electrodes in the first HCCD 14a is different from that in the second HCCD 14b. In the drawing, the H2 electrode 7 around the center in left and right directions is electrically connected with two electrodes 6 on left and right sides of the H2 electrode 7. Assuming those three electrodes as a center, on the left side of the drawing, the electrode 6 and the electrode 7 on the right side are electrically connected in the first HCCD 14a, and on the right side of the drawing, the electrode 6 and the electrode 7 on the left side are electrically connected in the second HCCD 14b. 
FIG. 19 is a diagram for explaining a driving method of the first HCCD 14a and the second HCCD 14b in the conventional solid state imaging apparatus 10 shown in FIG. 15. In the drawing, a timing chart is on the left side, and an electric potential diagram of the impurity layers 3 and 4 in FIG. 18 corresponding to the timing chart is on the right side.
The signal electric charges transferred from the VCCD 12 are temporally accumulated in the impurity layer 3 under the electrode 6 via the impurity layer 4 under the electrode 7. The signal electric charges are transferred to the left direction by the HCCD 14a and to the right direction by the HCCD 14b by the well-known inverted clock movement of the φH1 and φH2 as shown in the timing chart.
FIG. 20 is a schematic plan view of a border between the HCCD 14a and 14b including the vertical CCD (VCCD) 12 in the conventional solid state imaging apparatus 20.
Structural difference from the conventional solid state imaging apparatus 10 shown in FIG. 17 and FIG. 18 is that the electrodes 7 and 8 of in the HCCD 14 corresponding to the number of horizontal columns of the transfer circuits in the VCCD 12 is half, that a line memory (LM) 13 is positioned at a connecting part between the VCCD 12 and the HCCD 14, and the electrical connection of the HCCD 14.
That is, in the electrodes except the boundary of the first HCCD 14a and the second HCCD 14b, the electrodes 7 and the electrodes 6 are alternatively arranged. When a combination of the electrode 6 and the electrode 7 is defined as one unit, the number of the columns (the pairs) is twice of the number of the columns of the VCCD 12 in the conventional solid state imaging apparatus 10; however, the number of the columns (the pairs) is the same as the number of the columns of the VCCD 12 in the conventional solid state imaging apparatus 20. This is because that the line memory (LM) 13 is installed at the connecting part between the VCCD 12 and the HCCD 14 (the first HCCD 14a and the second HCCD 14b). That is, when the line memory is installed, only the signal electric charges in the columns (H1) connected with the line memory 13 can selectively be read to the HCCD 14 by setting H1 of the HCCD electrode to high electric potential and H2 of the HCCD to low electric potential while setting a condition of the line memory 13 to change from high electric potential to low electric potential. Only the signal electric charges in the columns (H2) connected with the line memory 13 can selectively be read to the HCCD 14 by setting H2 of the HCCD electrode to high electric potential and H1 of the HCCD to low electric potential while setting the line memory 13 from a state of high electric potential to low electric potential after transferring the signal electric charges in the HCCD 14. Then, all the signal electric charges can be read by transferring the signal electric charges in the HCCD 14. By the way, the border electrode 6 between the first HCCD 14a and the second HCCD 14b is H3.
FIG. 21 is a cross sectional view of a part cut across a line A-B in FIG. 20.
A basic structure is the same as that of the solid state imaging apparatus 10 shown in FIG. 18, and explanation will be omitted. The difference from the solid state imaging apparatus 10 is that the border electrode 6 between the first HCCD 14a and the second HCCD 14b is independent as the H3 electrode.
FIG. 22A and FIG. 22B are diagrams for explaining a driving method of the first HCCD 14a and the second HCCD 14b in the conventional solid state imaging apparatus 20 shown in FIG. 20. In the drawing, a timing chart is on the left side, and an electric potential diagram of the impurity layers 3 and 4 in FIG. 21 corresponding to the timing chart is on the right side.
The signal charges transferred from the VCCD 12 are temporally accumulated in the impurity layer 3 under the electrode 6 via the impurity layer 4 under the electrode 7. The signal electric charges are transferred to the left direction by the HCCD 14a and to the right direction by the HCCD 14b by the well-known inverted clock movement of the φH1 and φH2 as shown in the timing chart.
The above-described conventional solid state imaging apparatuses 10 and 20 need to drive both of the first HCCD 14a and the second HCCD 14b for obtaining image information of the whole part of the imaging area in the solid state imaging apparatuses even if vertical thinning out (execution to read out by a few lines) is executed by the VCCD 12.
FIG. 23 is a schematic view of the peripheral circuit regarding to output of the solid state imaging apparatus. In the drawing, output from an amplifier 15a is OS1, and output from an amplifier 15b is OS2.
Each of the outputs OS1 and OS2 is input to a correction and synthesizing circuit 22 via an analogue front end (AFE) 21 including a current buffer, a CDS circuit and an A/D converter. Since the property of the outputs differ depending on the difference in a physical position of the amplifier and dispersion on manufacturing, the outputs OS1 and OS2 need to input to the correction circuit to unite both properties. The OS1 and OS2 are synthesized after the correction and are output to a storage/monitor 24 after converting to output for colorizing process, storage format and monitor format by a digital signal processor (DSP) 23.
Moreover, the details of the prior art can be found in Japanese Laid-Open Patent 2004-194023.
As described in the above, in the conventional solid state imaging apparatus equipped with two HCCD, two types of HCCD must be driven at anytime when all the signal electric charges are read out, or when, for example, signals for AE/AF is obtained by thinning out the vertical signals or horizontal signals at a time for using a digital still camera. Therefore, the output amplifiers having large power consumption in the solid state imaging apparatus are always driven in two lines, and the power consumption will be large.
Also, in processing an output signal, the two AFE 21 need to be operated in order to process the output of the two lines of output amplifiers. Moreover, since the correction circuit 22 needs to be operated, it will cause increase in power consumption on the peripheral circuit. Moreover, it is considered that degradation of S/N ratio may be caused by correction error of the two lines.